Embedded computing [electronic resource] : a VLIW approach to architecture, compilers and tools / Joseph A. Fisher, Paolo Faraboschi, Cliff Young.

Includes bibliographical references and index.

Available through the EBSCO e-book Collection, which can be found on the Davenport University Library database page.

Cover -- About the Authors -- Foreword -- Contents -- Preface -- Content and Structure -- The VEX (VLIW Example) Computing System -- Audience -- Cross-cutting Topics -- How to Read This Book -- Figure Acknowledgments -- Acknowledgments -- CHAPTER 1 An Introduction to Embedded Processing -- 1.1 What Is Embedded Computing? -- 1.1.1 Attributes of Embedded Devices -- 1.1.2 Embedded Is Growing -- 1.2 Distinguishing Between Embedded and General-Purpose Computing -- 1.2.1 The "Run One Program Only" Phenomenon -- 1.2.2 Backward and Binary Compatibility -- 1.2.3 Physical Limits in the Embedded Domain -- 1.3 Characterizing Embedded Computing -- 1.3.1 Categorization by Type of Processing Engine -- 1.3.2 Categorization by Application Area -- 1.3.3 Categorization by Workload Differences -- 1.4 Embedded Market Structure -- 1.4.1 The Market for Embedded Processor Cores -- 1.4.2 Business Model of Embedded Processors -- 1.4.3 Costs and Product Volume -- 1.4.4 Software and the Embedded Software Market -- 1.4.5 Industry Standards -- 1.4.6 Product Life Cycle -- 1.4.7 The Transition to SoC Design -- 1.4.8 The Future of Embedded Systems -- 1.5 Further Reading -- 1.6 Exercises -- CHAPTER 2 An Overview of VLIW and ILP -- 2.1 Semantics and Parallelism -- 2.1.1 Baseline: Sequential Program Semantics -- 2.1.2 Pipelined Execution, Overlapped Execution, and Multiple Execution Units -- 2.1.3 Dependence and Program Rearrangement -- 2.1.4 ILP and Other Forms of Parallelism -- 2.2 Design Philosophies -- 2.2.1 An Illustration of Design Philosophies: RISC Versus CISC -- 2.2.2 First Definition of VLIW -- 2.2.3 A Design Philosophy: VLIW -- 2.3 Role of the Compiler -- 2.3.1 The Phases of a High-Performance Compiler -- 2.3.2 Compiling for ILP and VLIW -- 2.4 VLIW in the Embedded and DSP Domains -- 2.5 Historical Perspective and Further Reading -- 2.5.1 ILP Hardware in the 1960s and 1970s -- 2.5.2 The Development of ILP Code Generation in the 1980s -- 2.5.3 VLIW Development in the 1980s -- 2.5.4 ILP in the 1990s and 2000s -- 2.6 Exercises -- CHAPTER 3 An Overview of ISA Design -- 3.1 Overview: What to Hide -- 3.1.1 Architectural State: Memory and Registers -- 3.1.2 Pipelining and Operational Latency -- 3.1.3 Multiple Issue and Hazards -- 3.1.4 Exception and Interrupt Handling -- 3.1.5 Discussion -- 3.2 Basic VLIW Design Principles -- 3.2.1 Implications for Compilers and Implementations -- 3.2.2 Execution Model Subtleties -- 3.3 Designing a VLIW ISA for Embedded Systems -- 3.3.1 Application Domain -- 3.3.2 ILP Style -- 3.3.3 Hardware/Software Tradeoffs -- 3.4 Instruction-set Encoding -- 3.4.1 A Larger Definition of Architecture -- 3.4.2 Encoding and Architectural Style -- 3.5 VLIW Encoding -- 3.5.1 Operation Encoding -- 3.5.2 Instruction Encoding -- 3.5.3 Dispatching and Opcode Subspaces -- 3.6 Encoding and Instruction-set Extensions --T$1.

Description based on print version record.